1. Field of the Invention
The present invention relates to a decode device of a disk including a BCA (burst cutting area) area, a reproduction apparatus including the decode device, and a method for decoding.
2. Description of Related Art
FIG. 20 is a schematic diagram showing a BCA signal area on a disk. FIG. 21 is a diagram showing a format of data stored in a BCA of a DVD. As shown in FIG. 20, the BCA signal area is included in an inner peripheral side of the disk in a media such as DVD, HD DVD, and Blu-ray. Data is recorded in a radial direction in the BCA area by a barcode-like pattern having low reflectance formed by an intense laser in a manufacturing process. The time corresponding to 1T is determined by a standard for the interval between the lines having low reflectance in a certain number of rotations of a certain radius, and the interval width is regarded as the data.
It is needed to detect the head of the BCA signal area in order to obtain BCA information data. According to a related art, patterns of a synchronization pattern SBBCA shown in FIG. 21 are compared and detected to identify the head position of the information data. However, when the matching of the synchronization pattern is not detected due to the influence of a noise or the like, it is difficult to obtain the BCA information data.
In Japanese Unexamined Patent Application Publication No. 2004-47056 (Noro), two among SBBCA, Preamble, and RSBCA1 before the information data are detected to improve the accuracy of detecting the head position. FIG. 22 is a diagram showing a DVD reproduction apparatus disclosed by Noro.
As shown in FIG. 22, a decode device 100 includes a BCA decoding circuit 110, a buffering circuit 120, a buffering counter 125, and a BCA synchronization pattern detection circuit 130. The BCA decoding circuit 110 modulates and demodulates channel bits. The buffering circuit 120 buffers the channel bits. The buffering counter 125 monitors the buffering state of the buffering circuit. The BCA synchronization pattern detection circuit 130 detects the data having a predetermined value and detects data positional information of the channel data which is input.
The BCA synchronization pattern detection circuit 130 includes a ROM 131, a register 132, a comparison circuit 133, and a determination circuit 134. The ROM 131 stores a preamble data comparison pattern 131a and an ECC synch comparison pattern 131b. The register 132 is formed by a shift register for temporarily storing the channel bits. The comparison circuit 133 compares the channel bits with the comparing pattern. The determination circuit 134 detects the head of the BCA data based on the comparing result. The comparison circuit 133 includes a start synch comparison circuit 133a and an ECC synch comparison circuit 133b. The determination circuit 134 includes a start synch determination circuit 134a and an ECC area determination circuit 134b. 
Further, the DVD reproduction apparatus disclosed in Noro includes the decode device, an optical disk 201, a spindle motor 202 controlling the rotation, an optical head 203 radiating a laser beam, a pickup 204 receiving the reflection of the laser beam, a binary circuit 205 binarizing the reflected beam, a synchronous dynamic random access memory (SDRAM) 210 storing the output data of the decode device 100, and a central processing unit (CPU) 220 generally controlling the circuit in the reproduction apparatus.
The spindle motor 202 controls the rotation of the optical disk 201. The optical head 203 radiates a laser beam to the optical disk 201, and the reflection of the laser beam is received by the pickup 204. This received reflection is binarized by the binary circuit 205 and is subjected to a demodulation process corresponding to RZ modulation to generate channel data. This channel data is input to the decode device 100.
The decode device 100 is a circuit decoding the reproduced data read out from the BCA of the DVD to extract the synchronization information of the BCA data (identification data) recorded in the BCA. This output data is stored in the synchronous dynamic random access memory (SDRAM) 210. Note that the circuit such as the decode device 100 in the reproduction apparatus is generally controlled by the CPU 220.
The BCA decoding circuit 110 demodulates the phase-modulated channel data and performs decoding including error detection using the EDC in the demodulated data and syndrome calculation related with the error correction of the ECC. The central processing unit 220 performs the error correction of the ECC based on the result of the syndrome calculation.
On the other hand, the buffering circuit 120 buffers the input data when instructed to start buffering and outputs the buffered data to the SDRAM 210 every time the buffered data reaches a predetermined data amount (four bytes, for example). Note that the buffering counter 125 monitors the buffering state of the buffering circuit 120. The BCA synchronization pattern detection circuit 130 detects the data having the predetermined value and detects the data positional information of the input channel data.
The BCA synchronization pattern detection circuit 130 detects the data having the predetermined value of the data shown in FIG. 21 and detects the data positional information of the input channel data. To be more specific, the BCA synchronization pattern detection circuit 130 detects the synchronization pattern and the preamble data. Then the BCA synchronization pattern detection circuit 130 detects the six bytes of data (SBBCA, BCA Preamble, and RSBCA1) added in front of the information data shown in FIG. 21 and outputs a start trigger signal instructing the start of buffering with the buffering circuit 120. Further, a boundary between a fourth synchronization pattern (re-synch: RSBCA14) and a parity of the ECC shown in FIG. 21 is detected to output a stop trigger signal instructing the termination of buffering with the buffering circuit 120.
When a part of the data recorded in the BCA is missing or the noise is included in the reproduced data, the data may not be recognized as the synchronization pattern or the preamble data even when the synchronization pattern or the preamble data are input. In this case, it may be possible that the buffering cannot be started or the buffering is started at an abnormal timing. In order to prevent these problems, Noro discloses a technique of detecting the head of the BCA data (identification data) when the reproduced data matches at least two data of the reference patterns of a first synchronization pattern (SBBCA), preamble data (BCA Preamble), and a second synchronization pattern (RSBCA1).
Referring now to FIG. 23, a detection start procedure of the synchronization pattern disclosed in Noro will be described. As will be seen from FIG. 21, the data recorded in the BCA has one byte of the synchronization pattern added to the head of every four bytes of the information data. In the modulation processing that is executed to convert the information data into the recorded data (channel data), one bit is modulated to two bits. Since the recorded data is treated here, the data width of the standard in FIG. 21 is treated as doubled when the synchronization patterns are compared. For instance, one byte of synchronization pattern is treated as two bytes.
<1> Step SP101
A BCA binary signal (channel data) input to the buffering circuit 120 is input to the register 132.
<2> Step SP102
The channel data stored in the register 132 and the preamble data comparison pattern 131a are compared in the start comparison circuit 133a. In other words, the two bytes of the data at the head of the channel data stored in the register 132 is compared with the first synchronization pattern, and the eight bytes of data from the third byte to the tenth byte at the head of the channel data stored in the register 132 are compared with the data of the BCA preamble. Further, two bytes of data, the eleventh byte and the twelfth byte from the head of the channel data, stored in the register 132 are compared with the second synchronization pattern. The comparison here is performed until the channel data stored in the register 132 is matched with the preamble data comparison pattern 131a within the above margin of error.
<3> Step SP103
When any two or more of the first synchronization pattern, the BCA Preamble, and the second synchronization pattern match as a result of comparison at SP102, the data is regarded as the preamble data, and the process goes to <5>. When they do not match, the process goes to <4>.
<4> Step SP104
The register 132 is sequentially shifted by one bit unit, and the process goes to <1>.
<5> Step SP105
The start trigger signal is output from the start synch determination circuit 134a to the buffering circuit 120 or the BCA decoding circuit 110.
Referring now to FIG. 24, the completion of the detection of the synchronization pattern disclosed by Noro will be described. Since the recorded data is treated here as well, the data width of the standard in FIG. 21 is treated doubled when the synchronization patterns are compared.
<1> Step SP201
The BCA binary signal (channel data) input to the BCA decoding circuit 110 is input to the register 132.
<2> Step SP202
It is determined whether ten bytes of data are stored in the register 132. When the ten bytes of data are stored, the process goes to <3>. When the ten bytes of data are not stored, the process goes to <9>.
<3> Step SP203
The value +4 (corresponding to the information data after demodulation) is added to the buffering counter.
<4> Step SP204
The first two bytes of the data stored in the register 132 are compared with the ECC synch comparison pattern 131b. The comparison here is performed until the channel data stored in the register 132 is matched with the preamble data comparison pattern 131a within the above margin of error.
<5> Step SP205
When the comparing result indicates matching as a result of <4>, the step goes to <6>. When the result does not indicate matching, the step goes to <9>.
<6> Step SP206
The value +1 is added (incremented) to the ECC synch detection counter 136.
<7> Step SP207
When the buffering counter 125 is a multiple of 16, then the process goes to <8>. When the buffering counter 125 is not the multiple of 16, the process goes to <9>. The multiple of 16 means the boundary by the standard of the BCA forming the data structure for each four rows.
<8> Step SP208
When the ECC synch detection counter 136 is 2 or greater, the process is completed. When the ECC synch detection counter 136 is smaller than 2, the process goes to <9>. When the ECC synch detection counter 136 is 2 or greater, it means that the process is terminated when two or more than two among four ECC synch are detected.
<9> Step SP209
The register 132 is sequentially shifted by one bit unit, and the process goes to <1>.
It is necessary to obtain the BCA data in the Blu-ray disk. The BCA data needs to be obtained also in the DVD-R or the like since the DVD-R is CPRM-compatible. Therefore, a technique of contributing to improvement of the accuracy of obtaining the BCA data is needed. However, the accuracy of detecting the head of the BCA information data is degrading, which makes it difficult to obtain the BCA data.